1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including storage nodes with increased capacitance, and a method of manufacturing the same.
2. Description of the Related Art
Developments in manufacturing semiconductor devices have reduced the size of transistors and increased the integration density. For example large improvements have been made in the integration density of semiconductor memory devices such as dynamic random access memories (DRAMs). With modern methods, it is feasible to produce a 1-giga bit DRAM.
In general, DRAMs include cells each of which includes a single transistor. The cells in such devices can be categorized as either stack-type cells or trench-type cells, depending on the methods of forming the cell capacitor. In a DRAM with a stack-type cell, various approaches have been used to achieve a reduction in design rules and cell capacitors occupying a smaller area. For example, methods have been developed to increase the height of a storage node of a capacitor; to increase the effective surface area using hemi-spherical grains (HSG); and to utilize both the inward and the outward areas of one cylinder storage (OCS) capacitors. Devices with the OCS capacitors are particularly desirable in devices that use reduced design rules.
However, as is known, OCS capacitors sometimes cause twin bit failures. That is, as design rules are reduced, a cylindrical capacitor node is prone to fall down. The reason for this is that when storage nodes are disposed in a 2-dimensional shape, the distance between the storage nodes markedly decreases as design rules are reduced.
FIG. 1 is a schematic plan view of a conventional semiconductor device including conventional OCS-type capacitor storage nodes 50. The storage nodes 50 are disposed in a straight line pattern at right angles to the direction of bit lines 30 and word lines 20 (i.e., gate lines).
For a DRAM formed in the 0.1-μm regime, the area occupied by a storage node is estimated as follows. The length of each rectangular storage node is about 300 nm and the width thereof is about 120 nm. When the storage nodes 50 are disposed in a 2-dimensional shape, the distance between the storage nodes 50 is only about 50 nm. Thus, to obtain the capacitance required for a DRAM, the height of the storage node 50 must be not less than about 1500 nm.
The ratio of height to width of the cylindrical storage node 50 is 12 or higher. That is, since the storage node 50 has a very narrow width and a very high height, it is very prone to fall. If a storage node 50 leans toward the next storage node 50 or if it falls down, it may contact the next storage node 50 because distance between the nodes is only 80 nm. When the storage nodes 50 contact each other, twin bit failure occur. The storage nodes 50 are even more likely to fall down in the sub-0.1-μm regime.
The possibility that the storage nodes 50 will lean and contact the adjacent storage node depends on the arrangement of the storage nodes 50. Accordingly, methods for increasing distance between the storage nodes 50 by altering the arrangement have been proposed.
In the conventional device as shown in FIG. 1, from the plan view, the center of the storage node 50 naturally overlaps a plug-type conductive storage node contact 41, which is formed on an active region 11 of a semiconductor substrate. While the position of the storage node 50 can be altered, the center of the storage node 50 cannot depart from the storage node contact 41. Also, the conductive storage node contact 41 must be electrically isolated from the line contact 45, which is used to electrically connect a bit line 30 with the active region 11 of the semiconductor substrate. For these reasons, altering the position of the conductive storage node contact 41 is difficult.
Therefore, if one desires to change the arrangement of OCS-type storage nodes to prevent a storage node from leaning toward and contacting the next storage node, a new technique of maintaining contact resistance between the storage nodes and electrically connecting them with each other is desired. Also, it is desirable to increase the effective surface area of the storage node so as to secure sufficient capacitance. Even if it is possible to change the arrangement to prevent the storage node from falling down, with reduced design rules one must also take into account the fact that the storage nodes need sufficient effective surface area.